The present invention relates to a solid-state imaging apparatus. For example, the invention is appropriately applicable to a solid-state imaging apparatus having an integral analog/digital (A/D) converter.
A solid-state imaging apparatus of the related art includes multiple pixel circuits provided for multiple rows and columns, a reference voltage generation circuit, a counter, and an integral A/D converter provided for each column. The pixel circuit outputs an analog voltage whose level corresponds to an incident light quantity. The reference voltage generation circuit generates a reference voltage whose value linearly varies with a temporal change. The counter generates a counter code that linearly varies a count value with a temporal change at a specified cycle. The integral A/D converter latches a counter code in response to reversal of the high-low relationship of an analog voltage from the pixel circuit provided for a column corresponding to the reference voltage. The integral A/D converter outputs the latched counter code as a digital signal (e.g., refer to patent literature 1).
Each column may be provided with an up/down counter to calculate a difference between an analog voltage for imaging and an analog voltage for resetting (e.g., refer to patent literature 2).
The counter code may contain a low-order bit code and a high-order bit code. The low-order bit code includes multiple clock signals that differ from each other in phases. The high-order bit code includes a binary code whose count value varies synchronously with a clock signal. This solid-state imaging apparatus can improve the resolution without increasing a clock signal frequency (e.g., refer to patent literature 3).
Patent literature 4 describes a gray code counter that generates a gray code. The gray code changes only the logical level of a 1-bit signal during an increment (+1).